# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
--- |

  define void @false_s() {entry: ret void}
  define void @true_s() {entry: ret void}
  define void @uno_s() {entry: ret void}
  define void @ord_s() {entry: ret void}
  define void @oeq_s() {entry: ret void}
  define void @une_s() {entry: ret void}
  define void @ueq_s() {entry: ret void}
  define void @one_s() {entry: ret void}
  define void @olt_s() {entry: ret void}
  define void @uge_s() {entry: ret void}
  define void @ult_s() {entry: ret void}
  define void @oge_s() {entry: ret void}
  define void @ole_s() {entry: ret void}
  define void @ugt_s() {entry: ret void}
  define void @ule_s() {entry: ret void}
  define void @ogt_s() {entry: ret void}

  define void @false_d() {entry: ret void}
  define void @true_d() {entry: ret void}
  define void @uno_d() {entry: ret void}
  define void @ord_d() {entry: ret void}
  define void @oeq_d() {entry: ret void}
  define void @une_d() {entry: ret void}
  define void @ueq_d() {entry: ret void}
  define void @one_d() {entry: ret void}
  define void @olt_d() {entry: ret void}
  define void @uge_d() {entry: ret void}
  define void @ult_d() {entry: ret void}
  define void @oge_d() {entry: ret void}
  define void @ole_d() {entry: ret void}
  define void @ugt_d() {entry: ret void}
  define void @ule_d() {entry: ret void}
  define void @ogt_d() {entry: ret void}

...
---
name:            false_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: false_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
    ; FP32: $v0 = COPY [[ORi]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: false_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
    ; FP64: $v0 = COPY [[ORi]]
    ; FP64: RetRA implicit $v0
    %5:gprb(s32) = G_CONSTANT i32 0
    %4:gprb(s32) = COPY %5(s32)
    $v0 = COPY %4(s32)
    RetRA implicit $v0

...
---
name:            true_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: true_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
    ; FP32: $v0 = COPY [[ADDiu]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: true_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
    ; FP64: $v0 = COPY [[ADDiu]]
    ; FP64: RetRA implicit $v0
    %5:gprb(s32) = G_CONSTANT i32 -1
    %4:gprb(s32) = COPY %5(s32)
    $v0 = COPY %4(s32)
    RetRA implicit $v0

...
---
name:            uno_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: uno_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: uno_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(uno), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ord_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: ord_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ord_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(ord), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            oeq_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: oeq_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: oeq_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(oeq), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            une_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: une_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: une_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(une), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ueq_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: ueq_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ueq_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(ueq), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            one_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: one_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: one_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(one), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            olt_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: olt_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: olt_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(olt), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            uge_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: uge_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: uge_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(uge), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ult_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: ult_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ult_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(ult), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            oge_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: oge_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: oge_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(oge), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ole_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: ole_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ole_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(ole), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ugt_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: ugt_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ugt_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(ugt), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ule_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: ule_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ule_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(ule), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ogt_s
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $f12, $f14

    ; FP32-LABEL: name: ogt_s
    ; FP32: liveins: $f12, $f14
    ; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP32: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ogt_s
    ; FP64: liveins: $f12, $f14
    ; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
    ; FP64: [[COPY1:%[0-9]+]]:fgr32 = COPY $f14
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_S32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s32) = COPY $f12
    %1:fprb(s32) = COPY $f14
    %4:gprb(s32) = G_FCMP floatpred(ogt), %0(s32), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            false_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: false_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
    ; FP32: $v0 = COPY [[ORi]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: false_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
    ; FP64: $v0 = COPY [[ORi]]
    ; FP64: RetRA implicit $v0
    %5:gprb(s32) = G_CONSTANT i32 0
    %4:gprb(s32) = COPY %5(s32)
    $v0 = COPY %4(s32)
    RetRA implicit $v0

...
---
name:            true_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: true_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
    ; FP32: $v0 = COPY [[ADDiu]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: true_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
    ; FP64: $v0 = COPY [[ADDiu]]
    ; FP64: RetRA implicit $v0
    %5:gprb(s32) = G_CONSTANT i32 -1
    %4:gprb(s32) = COPY %5(s32)
    $v0 = COPY %4(s32)
    RetRA implicit $v0

...
---
name:            uno_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: uno_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: uno_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(uno), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ord_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: ord_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ord_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 1, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(ord), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            oeq_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: oeq_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: oeq_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(oeq), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            une_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: une_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: une_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 2, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(une), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ueq_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: ueq_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ueq_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(ueq), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            one_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: one_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: one_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 3, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(one), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            olt_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: olt_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: olt_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(olt), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            uge_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: uge_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: uge_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 4, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(uge), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ult_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: ult_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ult_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(ult), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            oge_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: oge_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: oge_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 5, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(oge), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ole_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: ole_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ole_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(ole), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ugt_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: ugt_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ugt_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 6, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(ugt), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ule_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: ule_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
    ; FP32: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVF_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ule_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
    ; FP64: [[MOVF_I:%[0-9]+]]:gpr32 = MOVF_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVF_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(ule), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
---
name:            ogt_d
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.1.entry:
    liveins: $d6, $d7

    ; FP32-LABEL: name: ogt_d
    ; FP32: liveins: $d6, $d7
    ; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
    ; FP32: [[COPY1:%[0-9]+]]:afgr64 = COPY $d7
    ; FP32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP32: FCMP_D32 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
    ; FP32: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP32: $v0 = COPY [[MOVT_I]]
    ; FP32: RetRA implicit $v0
    ; FP64-LABEL: name: ogt_d
    ; FP64: liveins: $d6, $d7
    ; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
    ; FP64: [[COPY1:%[0-9]+]]:fgr64 = COPY $d7
    ; FP64: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 1
    ; FP64: FCMP_D64 [[COPY]], [[COPY1]], 7, implicit-def $fcc0
    ; FP64: [[MOVT_I:%[0-9]+]]:gpr32 = MOVT_I $zero, $fcc0, [[ADDiu]]
    ; FP64: $v0 = COPY [[MOVT_I]]
    ; FP64: RetRA implicit $v0
    %0:fprb(s64) = COPY $d6
    %1:fprb(s64) = COPY $d7
    %4:gprb(s32) = G_FCMP floatpred(ogt), %0(s64), %1
    %3:gprb(s32) = COPY %4(s32)
    $v0 = COPY %3(s32)
    RetRA implicit $v0

...
